Constant-current LED drivers move current regulation and grayscale timing closer to the LEDs. The FPGA sends brightness words, controls shift and latch signals, and supplies any required grayscale clock. This tutorial uses TI’s TLC5940 and TLC5955 as concrete examples while keeping the controller architecture reusable.
Know what the driver provides
| Device | Channels | Grayscale | Serial rate |
|---|---|---|---|
| TLC5940 | 16 | 12 bit | Up to 30 MHz |
| TLC5955 | 48 | 16 bit | Up to 25 MHz |
The TLC5940 uses an external grayscale clock and exposes BLANK, XLAT, error, and programming-mode behavior. The TLC5955 adds 16-bit grayscale, per-color brightness controls, dot correction, error detection, and display-repeat features. The exact bit packing and edge timing come from the selected datasheet—not from a generic SPI assumption.
A reusable shift-and-latch engine
typedef enum logic [2:0] {IDLE, LOAD, CLK_HI, CLK_LO, LATCH, DONE} state_t;
always_ff @(posedge clk) begin
case (state)
IDLE: if (start) begin
shift_reg <= frame_data;
bit_count <= FRAME_BITS-1;
state <= LOAD;
end
LOAD: begin
sin <= shift_reg[bit_count];
sclk <= 1'b0;
state <= CLK_HI;
end
CLK_HI: begin
sclk <= 1'b1;
state <= CLK_LO;
end
CLK_LO: begin
sclk <= 1'b0;
if (bit_count == 0) state <= LATCH;
else begin bit_count <= bit_count - 1'b1; state <= LOAD; end
end
LATCH: begin
lat <= 1'b1;
state <= DONE;
end
DONE: begin
lat <= 1'b0;
done <= 1'b1;
state <= IDLE;
end
endcase
end
Parameterize frame width and bit order, then wrap the engine with a device-specific formatter. Register all outputs and constrain the interface as real external timing paths.
Initialization sequence matters
- Hold outputs blank while clocks and configuration stabilize.
- Program current range, brightness control, and dot correction before grayscale data.
- Load a known all-zero frame and latch it.
- Start the grayscale clock or display-repeat function.
- Release blanking only after a complete valid frame is active.
Electrical and thermal checks
The current-setting resistor, LED supply, output compliance voltage, simultaneous-channel current, package power dissipation, and PCB copper determine safe operation. Do not choose LED current from RTL. Calculate it from the device equations and verify worst-case thermal conditions.
Official datasheets
FPGA LED controller tutorial series
This article is part of the FPGA LED Controller Tutorials learning path. Continue with PWM vs. BCM, the HUB75 timing calculator, or SystemVerilog verification.
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