Center-Aligned vs. Edge-Aligned PWM on an FPGA

Two PWM engines can have the same frequency and duty cycle yet behave differently at their switching edges. Edge-aligned PWM places every rising edge at the period boundary. Center-aligned PWM moves both edges symmetrically around the center of the pulse. This tutorial implements both forms, explains the frequency math, and shows how to update duty cycle without producing runt pulses.

Edge-aligned PWM

VHDL-2008 reference implementation

This article uses synthesizable VHDL-2008. The complete tested VHDL bundle is linked below; adapt clock constraints, I/O standards, and timing parameters to the target board and panel.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity led_pwm is
  generic (BITS : positive := 8);
  port (
    clk       : in  std_logic;
    rst       : in  std_logic;
    level     : in  unsigned(BITS - 1 downto 0);
    pwm_out   : out std_logic
  );
end entity;

architecture rtl of led_pwm is
  signal counter      : unsigned(BITS - 1 downto 0) := (others => '0');
  signal active_level : unsigned(BITS - 1 downto 0) := (others => '0');
begin
  process (clk)
  begin
    if rising_edge(clk) then
      if rst = '1' then
        counter      <= (others => '0');
        active_level <= (others => '0');
      else
        counter <= counter + 1;
        if counter = 0 then
          active_level <= level;
        end if;
      end if;
    end if;
  end process;

  -- Maximum code intentionally means continuously on.
  pwm_out <= '1' when active_level = (active_level'range => '1') else
             '1' when counter < active_level else '0';
end architecture;

Download the VHDL-2008 FPGA LED controller examples

An up-counter starts at zero and the output is active while the counter is below the duty value. The carrier period is 2^B clocks for a B-bit counter.

Every active pulse begins at counter zero. That deterministic edge is convenient for triggering an ADC or logic analyzer, but simultaneous channels can switch together and create a larger instantaneous current step.

Center-aligned PWM

A triangular carrier counts up and then down. The compare threshold produces a pulse centered in the carrier cycle.

The triangular period is approximately twice the edge-aligned period for the same counter width, so compare frequencies only after accounting for the up-and-down traversal. Endpoint handling determines whether the exact count is 2(2^B−1) or another nearby value; specify it in the testbench.

When center alignment helps

• Symmetric edges are useful in motor-control and power-conversion timing.
• Multiple channels can be phase shifted to distribute switching current.
• Spectral energy differs from edge-aligned modulation, which may ease a particular EMI problem.
• For a simple status LED, edge-aligned PWM is usually smaller and easier to verify.

Verification checklist

• Measure the exact carrier period in clocks.
• Test duty values 0, 1, midscale, maximum−1, and maximum.
• Change the requested duty in the middle of a pulse and prove the active value changes only at the boundary.
• Assert complementary outputs never overlap if dead time is added.

Do not infer a gated fabric clock to implement either version. Use one real clock plus clock enables, and let the timing tools analyze the complete datapath.

Intel’s FPGA design recommendations provide broader guidance on clocking and RTL structure.