Center-Aligned vs. Edge-Aligned PWM on an FPGA

Two PWM engines can have the same frequency and duty cycle yet behave differently at their switching edges. Edge-aligned PWM places every rising edge at the period boundary. Center-aligned PWM moves both edges symmetrically around the center of the pulse. This tutorial implements both forms, explains the frequency math, and shows how to update duty cycle without producing runt pulses.

Edge-aligned PWM

An up-counter starts at zero and the output is active while the counter is below the duty value. The carrier period is 2^B clocks for a B-bit counter.

always_ff @(posedge clk) begin
    counter <= counter + 1'b1;
    if (counter == '0)
        active_duty <= requested_duty;
end

assign pwm_edge = (counter < active_duty);

Every active pulse begins at counter zero. That deterministic edge is convenient for triggering an ADC or logic analyzer, but simultaneous channels can switch together and create a larger instantaneous current step.

Center-aligned PWM

A triangular carrier counts up and then down. The compare threshold produces a pulse centered in the carrier cycle.

logic [BITS-1:0] carrier;
logic            counting_up;

always_ff @(posedge clk) begin
    if (rst) begin
        carrier    <= '0;
        counting_up <= 1'b1;
    end else if (counting_up) begin
        if (carrier == {BITS{1'b1}}) begin
            counting_up <= 1'b0;
            carrier <= carrier - 1'b1;
        end else carrier <= carrier + 1'b1;
    end else begin
        if (carrier == '0) begin
            counting_up <= 1'b1;
            active_duty <= requested_duty;
            carrier <= carrier + 1'b1;
        end else carrier <= carrier - 1'b1;
    end
end

assign pwm_center = (carrier < active_duty);

The triangular period is approximately twice the edge-aligned period for the same counter width, so compare frequencies only after accounting for the up-and-down traversal. Endpoint handling determines whether the exact count is 2(2^B−1) or another nearby value; specify it in the testbench.

When center alignment helps

• Symmetric edges are useful in motor-control and power-conversion timing.
• Multiple channels can be phase shifted to distribute switching current.
• Spectral energy differs from edge-aligned modulation, which may ease a particular EMI problem.
• For a simple status LED, edge-aligned PWM is usually smaller and easier to verify.

Verification checklist

• Measure the exact carrier period in clocks.
• Test duty values 0, 1, midscale, maximum−1, and maximum.
• Change the requested duty in the middle of a pulse and prove the active value changes only at the boundary.
• Assert complementary outputs never overlap if dead time is added.

Do not infer a gated fabric clock to implement either version. Use one real clock plus clock enables, and let the timing tools analyze the complete datapath.

Intel’s FPGA design recommendations provide broader guidance on clocking and RTL structure.