Ghost-Free Seven-Segment Display Controller on FPGA

A multiplexed seven-segment display looks simple until dim neighboring segments glow, digits smear during updates, or brightness changes with the number being shown. The fix is a disciplined scan sequence: blank, change the segment pattern, select the next digit, then enable light. This tutorial implements that sequence and adds per-display PWM brightness.

Understand the electrical polarity

The Basys 3 uses a four-digit common-anode display. Its digit enables and segment cathodes are active-low: drive one anode low to select a digit, and drive a segment line low to illuminate that segment. Other boards may be common-cathode, so put polarity conversion at the top level instead of burying it in the scan engine.

Choose a scan rate

If the controller visits four digits at a 4 kHz scan-event rate, each digit refreshes at 1 kHz. That leaves comfortable margin for human vision and many cameras. The segment duty cycle is about one quarter before global brightness PWM is applied.

Decode hexadecimal digits

function automatic logic [6:0] hex_segments(input logic [3:0] x);
    case (x)
        4'h0: hex_segments = 7'b1000000;
        4'h1: hex_segments = 7'b1111001;
        4'h2: hex_segments = 7'b0100100;
        4'h3: hex_segments = 7'b0110000;
        4'h4: hex_segments = 7'b0011001;
        4'h5: hex_segments = 7'b0010010;
        4'h6: hex_segments = 7'b0000010;
        4'h7: hex_segments = 7'b1111000;
        4'h8: hex_segments = 7'b0000000;
        4'h9: hex_segments = 7'b0010000;
        4'hA: hex_segments = 7'b0001000;
        4'hB: hex_segments = 7'b0000011;
        4'hC: hex_segments = 7'b1000110;
        4'hD: hex_segments = 7'b0100001;
        4'hE: hex_segments = 7'b0000110;
        default: hex_segments = 7'b0001110;
    endcase
endfunction

Blank before switching

always_ff @(posedge clk) begin
    if (scan_tick) begin
        if (!phase) begin
            an_n  <= 4'b1111;       // all digits off
            digit <= digit + 1'b1;
            seg_n <= hex_segments(value[digit*4 +: 4]);
            phase <= 1'b1;
        end else begin
            an_n  <= ~(4'b0001 << digit);
            phase <= 1'b0;
        end
    end
end

The explicit blank interval prevents the old segment pattern from appearing on the new digit. Because nonblocking assignments use old right-hand-side values, calculate the next digit in a temporary signal or update the index and pattern in separate states in production RTL.

Add brightness without breaking the scan

Keep scanning at a fixed rate and gate the selected anode with a higher-frequency PWM enable. Do not slow the scan to dim the display; that creates flicker. Latch brightness at a PWM boundary so one pulse cannot be truncated by a mid-period write.

Hardware checklist

• Confirm common-anode versus common-cathode polarity.
• Verify the A-through-G bit order against the schematic.
• Blank all digits during reset.
• Probe an enable and one segment together to confirm non-overlap.
• Use the board manufacturer’s pin constraints and I/O voltage.

Official reference

Digilent Basys 3 FPGA Board Reference Manual documents the common-anode display, active polarities, and package pins.